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| Features * Secure key storage to complement AT88SA100S and AT88SA102S Devices * Superior SHA-256 Hash Algorithm * Guaranteed Unique 48 bit Serial Number * High speed single wire interface, optionally shared with client * Supply Voltage: 2.5 - 5.5V * 1.8V - 5.5V communications voltage * <100nA Sleep Current * 4KV ESD protection * Multi-level hardware security * Secure personalization * Green compliant (exceeds RoHS) 3 pin SOT-23 package CryptoAuthenticationTM Host Security Chip AT88SA10HS Applications * Consumable device (battery, toner, other supplies) authentication * Network & Computer Access control * Authenticated communications for control networks * Anti-clone authentication for daughter cards * Physical access control (electronic lock & key) Preliminary 1. Introduction The CryptoAuthentication family of chips are the first cost-effective authentication devices to implement the SHA-256 hash algorithm, which is part of the latest set of recommended algorithms by the US Government. The 256 bit key space renders any exhaustive attacks impossible. The AT88SA10HS host version of CryptoAuthentication chips is capable of validating the response coming from the SHA-256 engine within an authentic CryptoAuthentication client (SA100S or SA102S), even if that response includes within the computation the serial number of the client. For detailed information on the cryptographic protocols, algorithm test values and usage models, refer to "AT88SA100S" and "AT88SA102S" Datasheets, along with the application notes dedicated to this product family. The host CryptoAuthentication performs 3 separate operations (named HOST0, HOST1 & HOST2) to implement this validation. The AT88SA10HS chip takes both the challenge and response as inputs and returns a single Boolean indicating whether or not the response is valid, in order to prevent the host chip from being used to model a valid client. The host system is responsible for generating the random challenge that is sent to both the client and host CryptoAuthentication devices as the AT88SA10HS does not include a random number generator. 8595B-SMEM-09/09 Note: The chip implements a failsafe internal watchdog timer that forces it into a very low power mode after a certain time interval regardless of any current activity. System programming must take this into consideration. Refer to 3.5 for more details. 1.1. Memory Resources Fuse Block of 128 fuse bits that can be written through the 1 wire interface. Fuse[87] has special meanings, see Section 1.2 for more details. Fuses[88:95] are part of the manufacturer ID value fixed by Atmel. Fuses[96:127] are part of the serial number programmed by Atmel which is guaranteed to be unique. See Section 1.3 for more details on the Manufacturing ID and Serial Number. Metal mask programmed memory. Unrestricted reads are permitted on the first 64 bits of this array. The physical ROM will be larger and will contain other information that cannot be read. The following three fields are stored in the ROM: ROM MfrID 2 bytes of ROM that specifies part of the manufacturing ID code. This value is assigned by Atmel and is always the same for all chips of a particular model number. For the AT88SA10HS, this value is 0xFF FF. ROM MfrID can be read by accessing ROM bytes 0 & 1 of Address 0. ROM SN 2 bytes of ROM that can be used to identify chips among others on the wafer. These bits reduce the number of fuses necessary to construct a unique serial number. The MaskSN is read by accessing ROM bytes 2 & 3 of Address 0. The serial number can always be read by the system but is never included in the message digested by the HOST command. 4 bytes of ROM that are used by Atmel to identify the model mask and/or design revision of the AT88SA10HS chip. These bytes can be freely read as the four bytes returned by ROM address 1, however system code should not depend on this value as it may change from time to time. ROM RevNum 1.2. Fuse Map The AT88SA10HS incorporates 128 one-time fuses within the chip. Once burned, there is no way to reset the value of a fuse. All fuses, with the exception of the Fuse MfrID and Fuse SN bits initialized by Atmel, have a value of 1 when shipped from the Atmel factory and transition to a 0 when they are burned. These fuses are burned at system personalization and cannot be changed after that time. Table 1. Fuse # 0 64 87 88 96 95 127 63 86 Fuse Map: Name Secret Fuses Status Fuses Fuse Enable Fuse MfrID Fuse SN Description These fuses can be securely written by the BurnSecure command but can never be read with the Read command These fuses can be written with the BurnSecure command and can always be read with the Read command. The HOST commands ignore the values of Fuse[0-63] until this bit is burned. Once this bit is burned, the BurnSecure command is disabled. See Section 1.3. Set by Atmel, can't be modified in the field See Section 1.3. Set by Atmel, can't be modified in the field 2 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] BurnSecure Enable This fuse is used to prevent repetitive operation of the two personalization commands: GenPersonalizationKey and BurnSecure. This fuse is always burned by the BurnSecure command. These 64 fuses are used to augment the mask programmed keys stored in the chip by Atmel. Knowledge of both the mask keys and the values of the Secret Fuses is required to calculate the response value expected by HOST2. The BurnSecure command can be used to burn an arbitrary selection of these 64 bits. These 23 fuses should be used to store information which is not secret, as their value can always be determined using the Read command. Typical usage would be model or configuration information. They cannot be automatically included in the messages to be hashed by the HOST commands, but the system may read them and pass them back to HOST1 in the input stream if desired. This fuse is used to prevent access to fuses on chips in which a partial set of fuses has been burned. This fuse must be burned using the BurnSecure command. Secret Fuses Status Fuses Fuse Enable 1.3. Chip Identification The chip includes a total of 72 bits of information that can be used to distinguish between individual chips in a reliable manner. The information is distributed between the ROM and fuse blocks in the following manner. Serial Number This 48 bit value is composed of ROM SN (16 bits) and Fuse SN (32 bits). Together they form a serial number that is guaranteed to be unique for all devices ever manufactured within the CryptoAuthentication family. This value is optionally included in the MAC calculation. Manufacturing ID This 24 bit value is composed of ROM MfrID (16 bits) and Fuse MfrID (8 bits). Typically this value is the same for all chips of a given type. It is always included in the cryptographic computations. 1.4. Key Values The values stored in the AT88SA10HS internal key array are hardwired into the masking layers of the chip during wafer manufacture. All chips have the same keys stored internally, though the value of a particular key cannot be determined externally from the chip. For this reason, customers should ensure that they program a unique (and secret) number into the 64 secret fuses and they should store the Atmel provided key values securely. Individual key values are made available to qualified customers upon request to Atmel and are always transmitted in a secure manner. When the serial number is included in the MAC calculation, the response is considered to be diversified and the host needs to know the base secret in order to be able to verify the authenticity of the client. A diversified response can also be obtained by including the serial number in the computation of the value written to the secret fuses. The Atmel AT88SA10HS provides a secure hardware mechanism to validate responses to determine if they are authentic. 1.5. SHA-256 Computation The AT88SA10HS performs only one cryptographic calculation - a keyed digest of an input challenge. It optionally includes various other information stored on the chip within the digested message. The AT88SA10HS computes the SHA-256 digest based on the algorithm documented here: http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf As a security measure, the 24 bit MfrID code (both ROM and Fuse bits) is automatically included in every message digested by the AT88SA10HS. The secret fuses are conditionally appended, depending on the parameters to the HOST command. For complete sample calculations, refer to"AT88SA100S" and/or "AT88SA102S" Datasheets. 3 8595B-SMEM-09/09 1.6. Security Features The AT88SA10HS incorporates a number of physical security features designed to protect the keys from release. These include an active shield over the entire surface of the part, internal memory encryption, internal clock generation, glitch protection, voltage tamper detection and other physical design features. Pre-programmed keys stored on the AT88SA10HS are encrypted in such a way as to make retrieval of their values via outside analysis very difficult. Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two signals. 2. IO Protocol Communications to and from the AT88SA10HS take place over a single asynchronously timed wire using a pulse count scheme. The overall communications structure is a hierarchy: Table 2. Tokens Flags Blocks Packets IO Hierarchy Implement a single data bit transmitted on the bus, or the wake-up event. Comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (if any) which may be transmitted. Data following the command and transmit flags. They incorporate both a byte count and a checksum to ensure proper data transmission. Bytes forming the core of the block without the count and CRC. They are either the input or output parameters of the AT88SA10HS command or status information from the AT88SA10HS. Refer to Applications Notes on Atmel's website for more details on how to use any microprocessor to easily generate the signaling necessary to send these values to the chip. 2.1. IO Tokens There are a number of IO tokens that may be transmitted along the bus: Input: (To AT88SA10HS) Wake Zero One ZeroOut OneOut Wake the AT88SA10HS up from sleep (low power) state Send a single bit from system to the AT88SA10HS with a value of 0 Send a single bit from system to the AT88SA10HS with a value of 1 Send a single bit from the AT88SA10HS to the system with a value of 0 Send a single bit from the AT88SA10HS to the system with a value of 1 Output: (From AT88SA10HS) The waveforms are the same in either direction, however there are some differences in timing based on the expectation that the host has a very accurate and consistent clock while the AT88SA10HS has significant variation in its internal clock generator due to normal manufacturing and environmental fluctuations. The bit timings are designed to permit a standard UART running at 230.4K baud to transmit and receive the tokens efficiently. Each byte transmitted or received by the UART corresponds to a single bit received or transmitted by the AT88SA10HS. Refer to Applications Notes on Atmel's website for more details. 4 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 2.2. AC Parameters WAKE tWLO tWHI data comm LOGIC O tSTART tZHI tZLO tBIT LOGIC 1 tSTART NOISE SUPPRESION tLIGNORE tHIGNORE 5 8595B-SMEM-09/09 Table 3. AC Parameters Direction To CryptoAuthentication To CryptoAuthentication To CryptoAuthentication From CryptoAuthentication To CryptoAuthentication From CryptoAuthentication To CryptoAuthentication From CryptoAuthentication To CryptoAuthentication Parameter Symbol Wake Low t WLO Duration Wake Delay to t WHI Data Comm. Start pulse t START duration Min Typ Max Unit Notes 60 s Signal can be stable in either high or low levels during extended sleep intervals. 1 ms Signal should be stable high for this entire duration. 4.1 4.34 4.56 s 4.62 6.0 8.6 s s s s s s If the bit time exceeds t TIMEOUT then CryptoAuthentication will enter sleep mode and the wake token must be resent. Zero transmission high pulse Zero transmission low pulse Bit time t ZHI 4.1 4.34 4.56 4.62 6.0 8.6 t ZLO 4.1 4.34 4.56 4.62 6.0 37.1 39 8.6 - t BIT Turn around delay t TURNAROUND From CryptoAuthentication From CryptoAuthentication To CryptoAuthentication 46.2 46.2 60 60 86 86 s s s CryptoAuthentication will initiate the first low going transition after this time interval following the end of the Transmit flag After CryptoAuthentication transmits the last bit of a block, system must wait this interval before sending the first bit of a flag Pulses shorter than this in width will be ignored by the chip, regardless of its state when active Pulses shorter than this in width will be ignored by the chip, regardless of its state when active Pulses shorter than this in width will be ignored by the chip when in sleep mode 46.2 60 86 High side t HIGNORE_A glitch filter @ active Low side glitch t LIGNORE_A filter @ active High side t HIGNORE_S glitch filter @ sleep Low side glitch t LIGNORE_S filter @ sleep IO Timeout t TIMEOUT To CryptoAuthentication To CryptoAuthentication To CryptoAuthentication To CryptoAuthentication To CryptoAuthentication 45 ns 45 ns 2 s s 2 7 10 13 Watchdog reset Pause Length t WATCHDOG t PAUSE To CryptoAuthentication - 3 18 4 25 5.2 32 Pulses shorter than this in width will be ignored by the chip when in sleep mode ms Starting as soon as 7ms up to 13ms after the initial signal transition of a token the chip will enter sleep if no complete & valid token is received. s Max. time from wake until chip is forced into sleep mode. Refer to Section 3.5 ms Duration during which the chip will ignore IO on the bus. See PauseShort command. START, ZLO, ZHI & BIT are designed to be compatible with a standard UART running at 230.4K baud for both transmit and receive. 6 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 3. DC Parameters Table 4. DC Parameters Parameter Operating temperature Power Supply Voltage Fuse Burning Voltage Active Power Supply Current Sleep Power Supply Current Input Low Voltage @ Vcc = 5.5V Input Low Voltage @ Vcc = 2.5V Input High Voltage @ Vcc = 5.5V Input High Voltage @ Vcc = 2.5V Input Low Voltage when Active Input High Voltage when Active Output Low voltage Output Low current Maximum Input Voltage ESD Symbol Min -40 2.5 3.0 Typ Max 85 5.5 5.5 Unit C V V mA Notes TA Vcc VBURN ICC Voltage is applied to Vcc pin - 10 I SLEEP 100 nA When chip is in sleep mode, Vcc = 3.7V, Vsig = 0.0 to 0.5V or Vsig = Vcc-0.5V to Vcc. Voltage levels for wake token when chip is in sleep mode Voltage levels for wake token when chip is in sleep mode Voltage levels for wake token when chip is in sleep mode Voltage levels for wake token when chip is in sleep mode When chip is in active mode, Vcc = 2.5 - 5.5V When chip is in active mode, Vcc = 2.5 - 5.5V When chip is in active mode, Vcc = 2.5 - 5.5V When chip is in active mode, Vcc = 2.5 - 5.5V, VOL = 0.4V VIL VIL VIH VIH VIL VIH VOL IOL VMAX V ESD -0.5 -0.5 .25 * Vcc 1.0 -0.5 1.2 .15 * Vcc 0.5 6.0 3.0 0.5 6.0 0.4 4 Vcc + 0.5 4 V V V V V V V mA V KV Human Body Model, Sig & Vcc pins. 7 8595B-SMEM-09/09 3.1. IO Flags The system is always the bus master, so before any IO transaction, the system must send an 8 bit flag to the chip to indicate the IO operation that is to be performed, as follows: Value 0x66 0x99 0xCC Name Command Transmit Sleep Meaning After this flag, the system starts sending a command block to the chip. The first bit of the block can follow immediately after the last bit of the flag. After a turn-around delay, the chip will start transmitting the response for a previously transmitted command block. Upon receipt of a sleep flag, the chip will enter a low power mode until the next wake token is received. All other values are reserved and will be ignored. Note that the values of flag for the AT88SA10HSS host are different from that of the two clients, the AT88SA100S and AT88SA102S. In this manner, both the AT88SA102S (or AT88SA100S) and AT88SA10HSS can share the same communications pin on the system controller. While the AT88SA10HS will wake up when communications are sent to the client, it will ignore all such transactions. It is possible that data values transmitted to a client authentication chip (either theAT88SS100S or the AT88SA102S) could be interpreted by the AT88SA10HS host chip as a legal transmit flag. In this case there could be a bus conflict as both the host and client chips drive the signal wire at the same time. To prevent this, the PauseShort command should be used to prevent the AT88SA10HS host chip from looking at the signal wire during any IO transaction to the client. 3.1.1. Command Timing After a command flag is transmitted, a command block should be sent to the chip. During parsing of the parameters and subsequent execution of a properly received command, the chip will be busy and not respond to transitions on the signal pin. The delays for these operations are listed in the table below: Table 5. Command Timing Symbol t PARSE t EXEC_HOST t EXEC_READ t EXEC_SECURE t PERSON Min Max 0 15 50 13 7 50 30 100 26 15 Unit s ms s ms ms Notes Delay to check CRC and parse opcode and parameters before an error indication will be available Delay to execute any of the 4 HOST commands Delay to execute Read command Max delay to execute BurnSecure command at Vcc > 4.5V. See Section 4.6 for more details. Delay to execute GenPersonalizationKey Parameter Parsing Delay HostDelay MemoryDelay SecureDelay PersonalizeDelay In this document, t chip. EXEC is used as shorthand for the delay corresponding to whatever command has been sent to the 8 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 3.1.2. Transmit Flag The transmit flag is used to turn around the signal so that the AT88SA10HS can send data back to the system, depending on its current state. The bytes that the AT88SA10HS returns to the system depend on its current state as follows: Table 6. Return Codes Error/Status 0x11 - Description Indication that a proper wake token has been received by the AT88SA10HS. Return bytes per "Output Parameters" in Command section of this document. In some cases this is a single byte with a value of 0x00 indicating success. The transmit flag can be resent to the AT88SA10HS repeatedly if a re-read of the output is necessary. Command was properly received but could not be executed by the AT88SA10HS. Changes in the AT88SA10HS state or the value of the command bits must happen before it is re-attempted. Command was NOT properly received by the AT88SA10HS and should be re-issued by the system. No attempt was made to execute the command. State Description After wake, but prior to first command After successful command execution Execution error 0x0F After CRC or other communications error 0xFF The AT88SA10HS always transmits complete blocks to the system, so in the above table, the status/error bytes result in 4 bytes going to the system - count, error, CRC x 2. After receipt of a command block, the AT88SA10HS will parse the command for errors, a process which takes tPARSE (Refer to 3.1.1). After this interval the system can send a transmit token to the AT88SA10HS - if there was an error, the AT88SA10HS will respond with an error code. If there is no error, the AT88SA10HS internally transitions automatically from t PARSE to t EXEC and will not respond to any transmit tokens until both delays are complete. 3.1.3. Sleep Flag The sleep flag is used to transition the AT88SA10HS to the low power state, which causes a complete reset of the AT88SA10HS's internal command engine and input/output buffer. It can be sent to the AT88SA10HS at any time when the AT88SA10HS will accept a flag. To achieve the specified I SLEEP, Atmel recommends that the input signal be brought below VIL when the chip is asleep. To achieve I SLEEP if the sleep state of the input pin is high, the voltage on the input signal should be within 0.5V of VCC to avoid additional leakage on the input circuit of the chip. The system must calculate the total time required for all commands to be sent to the AT88SA10HS during a single session, including any inter-bit/byte delays. If this total time exceeds t WATCHDOG then the system must issue a partial set of commands, then a Sleep flag, then a Wake token, and finally after the wake delay, issue the remaining commands. 9 8595B-SMEM-09/09 3.2. IO Blocks Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way: Byte Number 0 Name Count Meaning Number of bytes to be transferred to the chip in the block, including count, packet and checksum, so this byte should always have a value of (N+1). The maximum size block is 39 and the minimum size block is 4. Values outside this range will cause unpredictable operation. Command, parameters and data, or response. Refer to Section 3.1.2 & Section 4 for more details. CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial register value should be 0 and after the last bit of the count and packet have been transmitted the internal CRC register should have a value that matches that in the block. The first byte transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is the most significant byte of the CRC. 1 to (N-2) Packet N-1, N Checksum 3.3. IO Flow The general IO flow for the commands is as follows: System sends Wake token. System sends Transmit flag. Receive 0x11 value from the AT88SA10HS to verify proper wakeup synchronization. System sends Command flag. System sends complete command block. System waits t PARSE for the AT88SA10HS to check for command formation errors. System sends Transmit flag. If command format is OK, the AT88SA10HS ignores this flag because the computation engine is busy. If there was an error, the AT88SA10HS responds with an error code. 8. System waits t EXEC, Refer to Section 3.1.1. 9. System sends Transmit flag. 10. Receive output block from the AT88SA10HS, system checks CRC. 11. If CRC from the AT88SA10HS is incorrect, indication transmission error, system resends Transmit flag. 12. System sends sleep flag to the AT88SA10HS. Where the command in question has a short execution delay the system should omit steps 6, 7 & 8 and replace this with a wait of duration t PARSE + t EXEC. 1. 2. 3. 4. 5. 6. 7. 3.4. Synchronization Because the communications protocol is half duplex, there is the possibility that the system and the AT88SA10HS will fall out of synchronization with each other. In order to speed recovery, the AT88SA10HS implements a timeout that forces the AT88SA10HS to sleep. 10 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 3.4.1. IO Timeout After a leading transition for any data token has been received, the AT88SA10HS will expect another token to be transmitted within a tTIMEOUT interval. If the leading edge of the next token is not received within this period of time, the AT88SA10HS assumes that the synchronization with the host is lost and transitions to a sleep state. After the AT88SA10HS receives the last bit of a command block, this timeout circuitry is disabled. If the command is properly formatted, then it is re-enabled with the first transmit token that occurs after tPARSE + tEXEC. If there is an error in the command, then it is re-enabled with the first transmit token that occurs after tPARSE. In order to limit the active current if the AT88SA10HS is inadvertently awakened, the IO timeout is also enabled when the AT88SA10HS wakes up. If the first token does not come within the tTIMEOUT interval, then the AT88SA10HS will go back to sleep without performing any operations. 3.4.2. Synchronization Procedures When the system and the AT88SA10HS fall out of synchronization, the system will ultimately end up sending a transmit flag which will not generate a response from the AT88SA10HS. The system should implement its own timeout which waits for tTIMEOUT during which time the AT88SA10HS should go to sleep automatically. At this point, the system should send a Wake token and after tWLO + tWHI, a Transmit token. The 0x11 status indicates that the resynchronization was successful. It may be possible that the system does not get the 0x11 code from the AT88SA10HS for one of the following reasons: 1. 2. The system did not wait a full tTIMEOUT delay with the IO signal idle in which case the AT88SA10HS may have interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the tTIMEOUT delay and re-issue the Wake token. The AT88SA10HS went into the sleep mode for some reason while the system was transmitting data. In this case, the AT88SA10HS will interpret the next data bit as a wake token, but ignore some of the subsequently transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a correct CRC. Recommended resolution is to wait the tTIMEOUT delay and re-issue the Wake token. There are some internal error conditions within the AT88SA10HS which will be automatically reset after a t WATCHDOG interval, see below. There is no way to externally reset the AT88SA10HS - the system should leave the IO pin idle for this interval and issue the Wake token. 3. 3.5. Watchdog Failsafe After the Wake token has been received by the AT88SA10HS, a watchdog counter is started within the chip. After t WATCHDOG, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again. This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state machines of the AT88SA10HS including any IO synchronization issue, power consumption will fall to the low sleep level automatically. 3.6. Byte & Bit Ordering The AT88SA10HS is a little-endian chip: * All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order received. * Data is transferred to/from the AT88SA10HS least significant bit first on the bus. * In this document, the most significant bit and/or byte appears towards the left hand side of the page. 11 8595B-SMEM-09/09 4. Commands The command packet is broken down in the following way: Byte 0 1 2-3 4+ Name Opcode Param1 Param2 Data Meaning The Command code The first parameter - always present The second parameter - always present Optional remaining input data If a command fails because the CRC within the block is incorrect or there is some other communications error, then immediately after t PARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be all 1's. In this situation, the system should re-transmit the command block including the proceeding Transmit flag - providing there is sufficient time before the expiration of the watchdog timeout. If the opcode is invalid, one of the parameters is illegal, or the AT88SA10HS is in an illegal state for the execution of this command, then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be 0x0F. In this situation, the condition must be corrected before the (modified) command is sent back to the AT88SA10HS. If a command is received successfully, the system will be able to retrieve the output block as described in the individual command descriptions below after the appropriate execution delay. In the individual command description tables following, the "Size" column describes the number of bytes in the parameter documented in each particular row. The total size of the block for each of the commands is fixed, though that value is different for each command. If the block size for a particular command is incorrect, the chip will not attempt the command execution and returns an error. 12 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 4.1. HOST0 Concatenates the key stored in the AT88SA10HS with an input 256 bit challenge and generates the digest of this message. The result is left in internal memory and cannot be read. In general, the challenge should be a random number generated by the host system, which will be sent to both the host (AT88SA10HS) and client (AT88SA100S or AT88SA102S). Table 7. Input Parameters Name Opcode Param1 Param2 Data HOST0 Overwrite KeyID Challenge Size 1 1 2 32 0x08 If non-zero, overwrite part of internally generated key with secret fuses The internal key to be used to generate the digest. Challenge to be sent to the client AT88SA100S or AT88SA102S. Notes Table 8. Name Success Output Parameters Size 1 Notes Upon successful completion of HOST0, a value of 0 will be returned by the AT88SA10HS. The 512 bit message block that will be hashed with the SHA-256 algorithm will consist of: 256 bits 256 bits key[KeyID] challenge If the overwrite parameter is 0, then the 512 bit message block that will be hashed using the SHA-256 algorithm will consist of 256 bits 256 bits key[KeyID] challenge If the overwrite parameter has a value of 0x01, then the 512 bit message block that will be hashed using the SHA-256 algorithm will consist of 192 bits 64 bits 256 bits key[KeyID] Fuse[0-63] challenge All other values of the overwrite parameter are not recommended for use. 13 8595B-SMEM-09/09 4.2. HOST1 Completes the two block SHA-256 digest started by HOST0 and leaves the resulting digest within the internal memory of the AT88SA10HS. This command returns an error if HOST0 has not been successfully run previously within this wake cycle. As a security precaution, this command does not return the digest. A subsequent command is required to compare the response generated by the client with the one generated by the host. Table 9. Input Parameters Name Opcode Param1 Param2 Data Table 10. Name Success HOST1 Mode Zero OtherInfo Output Parameters Size 1 Notes Upon successful completion of HOST1, a value of 0 will be returned by AT88SA10HS. Size 1 1 2 13 0x40 Controls composition of message, see below for details. Must be 0x00 00 Input portion of message to be digested. Notes The contents of the second block to be digested are listed below. Note that to simplify this documentation; the bit addresses for OtherInfo are listed in the table below. Size 32 bits 64 bits 24 bits 8 bits 32 bits 16 bits 16 bits Source OtherInfo[0-31] Fuse[0-63] OtherInfo[32-55] Fuse[88-95] OtherInfo[56-87] ROM MfrID OtherInfo[88-103] Notes Opcode, param1 & param2 values sent to the AT88SA100S/AT88SA102S If enabled by bit 5 of the input mode parameter and if Fuse[87] is burned, else forced to 0 Status fuse values from AT88SA102S, or 0's Fuse MfrID, should match between AT88SA10HS and AT88SA100S/AT88SA102S. Fuse SN from AT88SA100S/AT88SA102S (Fuse[96-127]), or 0's Should match between AT88SA10HS and AT88SA100S/AT88SA102S. ROM SN from AT88SA100S/AT88SA102S, or 0's These bits are followed by the necessary `1' bit, `0' padding and 64 bit length as specified in the SHA-256 specification. 14 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] Mode Encoding Bit 5 of the mode is used to indicate whether or not the secret fuse bits are to be included in the calculation. The remaining bits of the mode field are ignored by the AT88SA10HS and should be 0. Table 11. Bit[5] 0 1 No fuse values inserted. Insert the values of Fuse[0-63] in the message. Mode Encoding Fuse Block If Fuse[87] has not been burned, then the values of Fuse[0-63] will be replaced by 0's in the above message generation step as a security measure. 15 8595B-SMEM-09/09 4.3. HOST2 Compares the value previously generated by the AT88SA10HS using HOST0 and HOST1 with that on the input stream coming from the client and returns status to indicate whether or not the two matched. This command returns an error if HOST1 has not been previously successfully run within this wake cycle. If the two digests do not match, the AT88SA10HS provides no information as to the source of the mismatch, which must be deduced from the inputs to the three HOSTX commands. On a match failure, the entire set of HOST0, HOST1 & HOST2 commands must be re-executed - HOST2 cannot be repeatedly executed. Table 12. Input Parameters Name Opcode Param1 Param2 Data Table 13. Name Success HOST2 Zero1 Zero2 ClientResponse Output Parameters Size 1 Notes If the input ClientResponse matches the internally generated response, a value of 0 will be returned by the AT88SA10HS after a THOST delay. If the two digests do NOT match, a value of 0x0F will be returned after a THOST delay. Size 1 1 2 32 0x80 Must be 0x00 Must be 0x00 00 Response from the client. Notes 16 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 4.4. Read Reads 4 bytes from Fuse or ROM. Returns an error if an attempt is made to read any fuses or ROM locations which are illegal. Table 14. Input Parameters Name Opcode Param1 Param2 Data Table 15. Name Contents Table 16. Name ROM Fuse Read Mode Address Ignored Output Parameters Size 4 Notes The contents of the specified memory location. Size 1 1 2 0 0x02 Fuse or ROM Which 4 bytes within array. Only bits 0 & 1 are used, all others must be 0's Notes Mode Encoding Value 0x00 0x01 Notes Reads four bytes from the ROM. Bit 1 of the address parameter must be 0. Reads the value of 32 fuses. Bit 1 of the address parameter must be 1. 17 8595B-SMEM-09/09 4.5. GenPersonalizationKey Loads a personalization key into internal memory and then uses that key along with an input seed to generate a decryption digest using SHA-256. Neither the key nor the decryption digest can be read from the chip. Upon completion, an internal bit is set indicating that a secure personalization digest has been loaded and is ready to use by the BurnSecure command. This bit is cleared (and the digest lost) when the watchdog timer expires or the power is cycled. This command will fail if Fuse[87] has been burned. Table 17. Input Parameters Name Opcode Param1 Param2 Data GenPers Zero KeyID Seed Size 1 1 2 16 0x20 Must be 0x00 Identification number of the personalization key to be loaded. Seed for digest generation. The least significant bit of the last byte is ignored by the AT88SA10HS. Notes Table 18. Name Success Output Parameters Size 1 Notes Upon successful execution, a value of 0 will be returned by the AT88SA10HS. The SHA-256 message body used to create the resulting digest internally stored in the chip consists of the following 512 bits: 256 bits 64 bits 127 bits 1 bits 64 bits PersonalizeKey[KeyID] Fixed value of all 1's Seed from input stream `1' pad length of message in bits, fixed at 512 18 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 4.6. BurnSecure Burns any combination of the first 88 fuse bits. Verification that the proper secret fuse bits have been burned must occur using the MAC command - there is no way to read the values in the first 64 fuses to verify their state. The 24 status fuses can be verified with the Read command. The fuses to be burned are specified by the 88 bit input map parameter. If a bit in the map is set to a `1', then the corresponding fuse is burned. If a bit in the map parameter is 0, then the corresponding fuse is left in its current state. The first bit sent to the AT88SA102S corresponds to Fuse[0] and so on up to Fuse[87]. Note that since a `1' bit in the Map parameter results in a `0' data value in the actual fuse array, the value in the Map parameter should be the inverse of the desired secret or status value. See Section 1.2 for more details. To facilitate secure personalization of the AT88SA102S, this map may be encrypted before being sent to the chip. If this mode is desired, then the Decrypt parameter should be set to 1 in the input parameter list. The decryption (transport) key is computed by the GenPersonalizationKey command, which must have been run immediately prior to the execution of BurnSecure. In this case, prior to burning any fuses, the input Map parameter is XOR'd with the first 88 bits of that digest from the GenPersonalizationKey command. The GenPersonalizationKey and BurnSecure commands must be run within a single wake cycle prior to the expiration of the watchdog timer. The power supply pin must meet the VBURN specification during the entire BurnSecure command in order to burn fuses reliably. If Vcc is greater than 4.5V, then the BurnTime parameter should be set to 0x00 and the internal burn time will be 250s. If Vcc is less than 4.5V but greater than VBURN then the BurnTime parameter should be set to 0x8000 and the internal burn time will be 190ms per fuse bit burned. The chip does NOT internally check the supply voltage level. The total BurnSecure execution delay is directly proportional to the total number of fuses being burned. If Vcc is less than 4.5V, then the total BurnSecure execution time may exceed the interval remaining before the expiration of the watchdog timer. In this case, the BurnSecure command should be run repeatedly, with each repetition burning only as many fuses as there is time available. The system software is responsible for counting the number of `1' bits in the clear-text version of the map parameter sent to the chip - no error is returned if the fuse burn count is too high. Other than Fuse[87] (see below), the fuses may be burned in any order. Prior to execution of BurnSecure, the AT88SA102S verifies that Fuse[87] is un-burned. If it has been burned, then the BurnSecure command will return an error. Fuse[87] must be burned during the last repetition of BurnSecure, optionally in combination with other fuses. There are a series of very small intervals during tEXEC_SECURE when the fuse element is actually being burned. The power supply must not be removed during this interval and the watchdog timer must not be allowed to expire during this interval, or the fuse may end up in a state where it reads as un-burned but cannot be burned. Table 19. Input Parameters Name Opcode Param1 Param2 Data Table 20. Name Success BURNSECURE Decrypt BurnTime Map Output Parameters Size 1 Notes Upon successful execution, a value of 0 will be returned by the AT88SA10HS. Size 1 1 2 11 0x10 If 1, decrypt Map data before usage. If 0, the map is transmitted in plain text. Must be 0x00 00 if Vcc > 4.5V, must be 0x80 00 otherwise. Which fuses to burn, may be encrypted. Notes This command takes a constant time to execute regardless of the number of fuses being burned. 19 8595B-SMEM-09/09 4.7. PauseShort Forces the chip into a busy mode for a period of t PAUSE. During execution of this command the chip will ignore all activity on the IO signal. This command is used to prevent bus conflicts in a system that also includes one or more AT88SA100S or AT88SA102S client chips sharing the same signal wire. Table 21. Input Parameters Name Opcode Param1 Param2 Data Table 22. Name Success PAUSESHORT Ignored Ignored Ignored Output Parameters Size 1 Notes After a delay of t PAUSE, the AT88SA10HSS will return a value of 0 in response to a transmit flag. Size 1 1 2 0 0x00 Must be 0x00 Must be 0x00 00 Notes 5. Pinout There are three pins on the chip. Table 23. Pin # 1 Chip Pins Name Signal Description IO channel to the system, open drain output. It is expected that an external pull-up resistor will be provided to pull this signal up to VCC for proper communications. When the chip is not in use this pin can be pulled to either VCC or VSS. Power supply, 2.5 - 5.5V. This pin should be bypassed with a high quality 0.1F capacitor close to this pin with a short trace to VSS. Refer to Applications Notes on Atmel's website for more details. Connect to system ground. 2 VCC 3 VSS 20 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 AT88SA10HS Host Authentication Chip [Preliminary] 6. Package Drawing 3TS1 - Shrink SOT 21 8595B-SMEM-09/09 7. Revision History Table 24. 8595A Revision History Date 04/2009 Initial document release. Comments Doc. Rev. 22 AT88SA10HS Host Authentication Chip [Preliminary] 8595B-SMEM-09/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support securemem@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, and others are registered trademarks, CryptoAuthenticationTM, and others, are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 8595A-SMEM-04/09 |
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